1. Field of the Invention
The present invention relates to a semiconductor capacitor, and more particularly, to a compact, three-terminal or multi-terminal metal-oxide-metal (MOM) capacitor.
2. Description of the Prior Art
Passive components such as capacitors are extensively used in integrated circuit (IC) design for radio-frequency (RF) and mixed-signal applications, such as bypassing, inter-stage coupling, and in resonant circuits and filters. One of the most commonly used capacitors is the metal-oxide-metal (MOM) capacitor.
FIG. 1 illustrates a typical MOM capacitor. As shown in FIG. 1, the MOM capacitor 10 includes interdigitated multi-fingers 12 and 14 that are formed in multiple metal layers. The interdigitated multi-fingers are optionally connected by vias 16 and 18 in the vertical BEOL (back-end-of-line) stack separated by inter-metal dielectrics (not explicitly shown). The fabricating process of an MOM capacitor can be integrated with the connect process. Hence, no extra photo mask is required. For example, the dual-damascene techniques typically used with copper multilevel connection metallization on ICs can be used to construct stacks of copper-filled vias and trenches. Two or more such copper-filled vias or trenches, separated by oxide dielectrics, form an MOM capacitor.
The above-mentioned typical MOM capacitors, however, are all two-terminal type MOM capacitors. In some circumstances, such as the equivalent circuit diagrams shown in FIG. 2 and FIG. 3, two discrete, two-terminal MOM capacitors 22 and 24 are typically required to constitute the circuit configuration indicated by the dotted line region 20. The two discrete MOM capacitors 22 and 24 employed in the aforesaid exemplary equivalent circuit diagrams occupy a relatively larger circuit floor plan. It is often desirable to reduce the on-chip circuit elements such as the MOM capacitor in order to reduce the circuit floor plan because reducing circuit floor plan can improve circuit density.